In this multi part tutorial we will explore one of my favorite microprocessors, the PicoBlaze. This is a little microprocessor designed and optimized for usage with FPGA’s from Xilinx. It’s easy to setup and easy to tweak (that’s why it’s one of my favorites)! In this first part we will talk about the PicoBlaze and it’s architecture. Enjoy!

The PicoBlaze

The PicoBlaze is a 8-bit microprocessor specially designed for the usage with Xilinx FPGA’s. In this section we are going to take a closer look to the block diagram of the PicoBlaze, it’s function blocks and how the PicoBlaze is interfaced with the FPGA. You’ll see that the way the PicoBlaze is build up isn’t that different from other small microprocessors. If you ever attended a computer architecture course or have done extended reading about microcontrollers then a lot of the functional blocks in the diagram should seem familiar.

Block diagram

The block Diagram of the PicoBlaze can be seen in the figure beneath:

The function blocks are the following:

  • General-Purpose Registers: the PicoBlaze contains 16-byte-wide-general-purpose registers which are addressed from s0 to sF.
  • Instruction Program Store: the memory of the PicoBlaze can contain up to 1024 instruction which can be executed. The instructions have a length of 18-bits.
  • Arithmetic Logic Unit (ALU): the ALU of the PicoBlaze is 8-bits (or a byte) wide and performs the calculations for the microprocessor. These calculation can contain basic arithmetic operations (addition, subtraction), bitwise logic operations (and, or and xor), arithmetic compare operations, bitwise test operations, comprehensive shift operations and rotate operations.
  • Flags: the operations done by the alu affect the zero and carry flag. The zero flag indicates when a result of the last operation resulted into 0. The carry flag on the other hand indicates various conditions depending on the last instruction executed. The interrupt enable flag enables the interrupt input (this is not enabled by default and should be done by the user).
  •  Scratchpad RAM: this RAM is 64-*byte wide and is directly or indirectly addressable from the registers via the “store” and “fetch”  instructions.
    • store writes the content of any of the 16 registers to any of the 64 RAM locations.
    • fetch read any of the 64 RAM locations into one of the 16 registers.
  • Input/Output: these ports allow the PicoBlaze to connect with custom peripherals or other FPGA’s. The PicoBlaze support up to 256 input port and 256 ouput ports or a combination of input/output ports.
  • Program Counter (PC): the Program Counter points to the next instruction that needs to be executed. When executing a instruction the PC will get incremented automatically and points to the next instruction location.
  • Interrupts: there is an optional interrupt input to the PicoBlaze. This gives the microprocessor the capability to handle asynchronous external events (of course every good designer should know that asynchronous events in a synchronous design are not done and you have to synchronize them).
  • Call/Return stack: this stack can store up to 31 instruction addresses which enables it to nested call sequences that are up to 31 levels deep. The stack is implemented as a circular buffer, when it’s full it will overwrite the oldest value.
  • Reset: after the PicoBlaze is loaded into the FPGA an automatic reset occurs and this forces the microprocessor after configuration into the initial state. In this state the PC is reset to address 0, all the flags are cleared, interrupts are disabled and the call/return stack is reset. The only thing not affected by the reset are the registers and the scratchpad RAM.

Interfacing the PicoBlaze

The interfacing of the PicoBlaze can be seen in the figure beneath:

We can separate this interface into two parts, the first part is the KCPM3 (Ken Chapman Programmable State Machine 3) and this is the processor itself.  It will execute all the different instruction that are fed into the processor. The ROM (Read-Only Memory), the instruction program store in the block diagram, contains all the different instructions which the processor can use. This ROM is written by the user in assembler and then converted into VHDL by a compiler (we will see in part III howto write a program for the PicoBlaze in assembler and compile it into VHDL).


A single interrupt input signal is provided on the PicoBlaze. The user has to enable this signal, since after the reset of the PicoBlaze the interrupt signal is turned off by default. If enabled by the user, the interrupt input signal should be high for at least two clock cycles. This way the PicoBlaze can guarantee that the interrupt is recognized, which is demonstrated in the figure below:

When an high signal is detected on the interrupt input port, the PicoBlaze is forces to execute the CALL 3FF instruction after finishing it’s current instruction. The 3FF instruction is a subroutine call to the last program memory location and defines how the application code should handle an interrupt. This is also called an Interrupt Service Routine or ISR for short.

It’s important that no other interrupts occurs during the interrupt handling process. Once the interrupt is handled, a special command ensures that the flags are restored, the controls for future interrupts are enabled and the PC values saved on the call/return stack are loaded back into the PC registers. When this is done the program flow returns back to the instruction following the instruction where the interrupt occurred.

Performance of the PicoBlaze

The processor and the ROM are connected to the clock of the FPGA. Every 2 clock cycles the PicoBlaze can execute 1 instruction. This results in a predictable execution performance for the designer of the system. It’s suggested by the PicoBlaze documentation that there is no need to operate the PicoBlaze at it’s maximum clock frequency (unless the application requires it). This is recommended due to the fact that the PicoBlaze is often managing slower peripherals like serial communication or monitoring keyboard buttons. A decrease in clock frequency will reduce the number of idle instruction cycles and reduces the total power consumption of the system. Therefore you should always think twice when you are designing a systems and what the goals of that system are. The table underneath shows the PicoBlaze performance using the slowest speed grade for a couple of different FPGA’s:

Further reading and what’s next

If you want to read in more depth about the PicoBlaze, I strongly advice to go to the site of Xilinx where you can read the user guide of the PicoBlaze. This documentation can be found with the following link: PicoBlaze Documentation. Take certainly a look at chapter 4: interrupts, and chapter 6: Input and Output Ports.

In the next part of this tutorial we are going to implement the PicoBlaze on a Digilent Nexys 4 FPGA, in preparation for the next part you can already download the PicoBlaze from Xilinx on the following link: PicoBlaze Design Files.







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